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KiviHash-HMAC-SHA512

Secure Keyed-Hash Message Authentication Code IP Core 

KiviHash-HMAC-SHA512 Overview 

The HMAC SHA-512 IP core enables secure Keyed-Hash Message Authentication Code (HMAC) generation using the SHA-512 algorithm. The IP core is compliant to NIST FIPS 198-1 and NIST SP 800-224. It features automatic padding and a high-speed architecture optimized for efficient processing in embedded systems. The core is designed as a fully synchronous module and supports integration via an AMBA® AXI4-Lite interface. To simplify system integration, it is delivered with a hardware abstraction layer (HAL) and platform-independent C-based software drivers. The design can be deployed on a wide range of FPGA and ASIC platforms. 

Key Features

  • NIST FIPS 198-1 and NIST SP 800-224 compliant
  • Supports Keyed-Hash Message Authentication Code (HMAC) using SHA-512
  • Supports HMAC for SHA-512, SHA-384, SHA-512/256
  • Automatic padding
  • High-speed design 
  • Fully synchronous design
  • HAL and software driver (C-code, platform independent)
  • For any FPGA and ASIC 

Tests and Verification

  • Extended verification through simulation
  • FPGA integration and implementation tests
  • Unity tests for driver and whole IP Core
Download product brief
HMAC_block_diagram.drawio (1)

 

Applications & Use Cases

  • Boot chains: Verifying firmware integrity from root of trust to application
  • Firmware Updates: Protection against unauthorized update
  • IPsec and TLS
     

     

Easy integration

  • AMBA® AXI4 lite Interface
  • Platform agnostic C source code HAL, API and software driver
  • Software examples included
  • Software user guide
  • Integration examples
  • Comprehensive documentation

Technical documentation & evaluation package

Register for the Evaluation Portal to access evaluation packages, technical documentation and integration resources.

 Register for the KiviCore Evaluation Portal to access the evaluation package, technical documentation and integration resources. 
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Licensing

Licensing & Deliverables

License type Purpose Scope Fee Deliverables
Product License Manufacture of products intended for commercial distribution. Valid for single-instance implementation/synthesis into one device (e.g., one type of SoC, or FPGA) for a specific project or product definition. Multiple instantiations refer to the physical realization of one IP core multiple times in one device. One-time fee 
  • System Verilog RTL Source Code or Netlist format
  • Testbenches
  • Integration examples
  • Simulation and synthesis scripts
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Evaluation License Usability and evaluation for upcoming design  Valid for single-instance implementation/synthesis into one device (SoC, or FPGA) for a specific upcoming design project. Free, no license fee
  • Netlist format, time-bombed
  • Testbenches
  • Integration examples
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Support and Maintenance

  • Maintenance and updates of IP core included

  • Rapid bug fix cycles
  • Documentation and integration examples included
  • Web based support with response times of 8 hours (Mo to Fri)

 

FPGA Implementation Results

AMD (Xilinx) Implementation Results

 

Device
 LUTs

max. Frequency (MHz)

 max. Throughput (Gbps)

Spartan 7

 3415 157.3 2.52

Kintex 7

 3418 267.5 4.28

Zynq US+ MPSoC

 3505 361.8 5.79

Versal AI Cores Series

 3210 446.4 7.14

 

Efinix Implementation Results

 

Device
 XLR

max. Frequency (MHz)

 max. Throughput (Gbps)

Titanium

 6018 258.1 4.56

Topaz

 6018 198.7 3.18

Trion

 6018 79.3 1.27