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KiviHash-HMAC-SHA256 | Secure Keyed-Hash Message Authentication Code IP Core 

IP Core Documentation

FPGA Implementation Results

 Licensing

KiviHash-HMAC-SHA256 Overview 

The HMAC SHA-256 IP core enables secure Keyed-Hash Message Authentication Code (HMAC) generation using the SHA-256 algorithm. The IP core is compliant to NIST FIPS 198-1 and NIST SP 800-224. It features automatic padding and a high-speed architecture optimized for efficient processing in embedded systems. The core is designed as a fully synchronous module and supports integration via an AMBA® AXI4-Lite interface. To simplify system integration, it is delivered with a hardware abstraction layer (HAL) and platform-independent C-based software drivers. The design can be deployed on a wide range of FPGA and ASIC platforms. 

Key Features

  • NIST FIPS 198-1 and NIST SP 800-224  compliant
  • Supports HMAC using SHA-256
  • Automatic padding
  • High-speed design
  • AMBA® AXI4-Lite interface
  • Fully synchronous design
  • HAL and software driver (C-code, platform independent)
  • For any FPGA and ASIC

Tests and Verification

  • Extended verification through simulation
  • FPGA integration and implementation tests
  • Unity tests for driver and whole IP Core
HMAC_block_diagram.drawio (1)

 

Applications & Use Cases

  • Boot chains: Verifying firmware integrity from root of trust to application
  • Firmware Updates: Protection against unauthorized updates
  •  IPsec and TLS 

     

Easy integration

  • AMBA® AXI4 lite Interface
  • Platform agnostic C source code HAL, API and software driver
  • Software examples included
  • Software user guide
  • Integration examples
  • Comprehensive documentation

Next Steps

Download the product brief, request documentation, or schedule a technical discussion to review your architecture.

Download product brief
Schedule a technical discussion

Request documentation

Product Information

Licensing & Deliverables
Strich-2-thick
License type Purpose Scope Fee Deliverables
Product License Manufacture of products intended for commercial distribution. Valid for single-instance implementation/synthesis into one device (e.g., one type of SoC, or FPGA) for a specific project or product definition. Multiple instantiations refer to the physical realization of one IP core multiple times in one device. Product licenses for IP Cores include volume caps of 10,000 units for FPGAs. One-time fee 
  • System Verilog RTL Source Code or Netlist format
  • Testbenches
  • Integration examples
  • Simulation and synthesis scripts 
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Evaluation License Usability and evaluation for upcoming design  Valid for single-instance implementation/synthesis into one device (SoC, or FPGA) for a specific upcoming design project. Free, no license fee
  • Netlist format, time-bombed
  • Testbenches
  • Integration examples
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Support and Maintenance
Strich-2-thick
  • Maintenance & updates of IP cores included
  • Rapid update/bug fix cycles
  • Integration support: Comprehensive documentation and integration examples 
  • Web-based support with response times within 8 hours (Mo-Fri)

FPGA Implementation Results

 

AMD (Xilinx) Implementation Results
 Strich-2-thick 
Device
 LUTs

max. Frequency (MHz)

 max. Throughput (Gbps)

Spartan 7

 1685 191.4 1.53

Kintex 7

 1685 308.6 2.47

Zynq US+ MPSoC

 1822 473.7 3.79

Versal AI Cores Series

 1761 496.8 3.97

 

 

Efinix Implementation Results
 Strich-2-thick 
Device
 XLR

max. Frequency (MHz)

 max. Throughput (Gbps)

Titanium

 3067 404.9 3.24

Topaz

 3067 286.5 2.29

Trion

 3067 116.2 0.93