KiviHash-SHA3 Overview
The KiviHash-SHA-3 (secure hash algorithms) is a hardware accelerator for cryptographic hashing functions. It is an area efficient and high throughput design and compliant to NIST’s FIPS 202 standard. It supports all SHA-3 hash functions (SHA-3-224, SHA-3-256, SHA-3-384 and SHA-3-512) as well as extendable output functions (XOF), SHAKE-128 and SHAKE-256. It provides full protection against time-based side channel attacks (SCA). Automatic byte padding is included. It operates in a single clock domain and has been extensively verified.
Key Features
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NIST FIPS 202 compliant
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Supports cryptographic hashing for SHA-3 in 224/256/384/512 mode
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Supports cryptographic hashing for Keccak in 224/256/384/512 mode
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Extendable-Output Functions for SHAKE 128/256
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AMBA® AXI4-Lite Interface
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Fully synchronous design
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HAL and software driver (C-code, platform independent)
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Platform agnostic design for any FPGA
Easy integration
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AMBA® AXI4 lite Interface
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Platform agnostic C source code HAL, API and software driver
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Software examples included
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Software user guide
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Integration examples
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Comprehensive documentation

Applications & Use Cases
The SHA-3 IP core offers a versatile solution for maintaining data integrity and verifying authentication across various applications.
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Firmware Updates: Detecting tampered or corrupted update packages
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FPGA bitstreams: Ensuring only trusted configurations are loaded
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External memory integrity: Protecting stored data in flash or external RAM
Test and Verification
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NIST CAVS test vectors for SHA3 hash functions
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NIST CAVS test vectors for SHA3 XOF functions
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Extended verification through simulation
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FPGA integration and implementation tests
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Unity tests for driver and whole IP Core
Technical documentation & evaluation package
Register for the Evaluation Portal to access evaluation packages, technical documentation and integration resources.
Licensing
Licensing & Deliverables
| License type | Purpose | Scope | Fee | Deliverables |
| Product License | Manufacture of products intended for commercial distribution. | Valid for single-instance implementation/synthesis into one device (e.g., one type of SoC, or FPGA) for a specific project or product definition. Multiple instantiations refer to the physical realization of one IP core multiple times in one device. | One-time fee |
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| Evaluation License | Usability and evaluation for upcoming design | Valid for single-instance implementation/synthesis into one device (SoC, or FPGA) for a specific upcoming design project. | Free, no license fee |
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Support and Maintenance
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Maintenance and updates of IP core included
- Rapid bug fix cycles
- Documentation and integration examples included
- Web based support with response times of 8 hours (Mo to Fri)
FPGA Implementation Results
AMD (Xilinx) Implementation Results
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Device
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LUTs |
max. Frequency (MHz) |
max. Throughput (Gbps) |
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Spartan 7 |
7687 | 171.5 | 8.4 |
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Kintex 7 |
7722 | 258.5 | 12.4 |
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Zynq US+ MPSoC |
7730 | 340.5 | 16.3 |
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Versal AI Cores Series |
7572 | 427.4 | 20.5 |
Efinix Implementation Results
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Device
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XLR |
max. Frequency (MHz) |
max. Throughput (Gbps) |
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Titanium |
9246 | 375.7 | 18.0 |
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Topaz |
9246 | 234.6 | 11.3 |
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Trion |
9246 | 102.9 | 4.9 |
