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SHA-3 Crypto Engine IP Core

SHA-3-Block-Diagram-1

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Overview 

The SHA-3 – secure hash algorithms – crypto engine is a hardware accelerator for cryptographic hashing functions. It is an area efficient and high throughput design and compliant to NIST’s FIPS 202 standard. Additionally it supports all SHA-3 hash functions – SHA-3-224, SHA-3-256, SHA-3-384 and SHA-3-512 – as well as extendable output functions (XOF) – SHAKE-128 and SHAKE-256. It provides full protection against time-based side channel attacks (SCA). Automatic byte padding is included.  It operates in a single clock domain and has been extensively verified. 
 
The SHA-3 IP core offers a versatile solution for maintaining data integrity and verifying authentication across various applications. Its applications span a wide range, including Message Authentication Codes (MAC), IPsec and TLS/SSL protocol engines, secure boot engines, encrypted data storage, e-commerce platforms, financial transaction systems, blockchain, or pseudo random bit generation.

Key Features

  • FIPS 202 compliant
  • Supports cryptographic hashing for SHA-3 in 224/256/384/512 mode
  • Extendable-Output Functions for SHAKE 128/256
  • AMBA® AXI4-Stream 
  • Fully synchronous design
  • For any FPGA and ASIC

Product Specifications

Deliverables

License type Purpose Scope Fee Deliverables
Product License Manufacture of products intended for commercial distribution. Valid for single-instance implementation/synthesis into one device (e.g., one type of SoC, or FPGA) for a specific project or product definition. Multiple instantiations refer to the physical realization of one IP core multiple times in one device. Product licenses for IP Cores include volume caps of 10,000 units for FPGAs. One-time fee 
  • System Verilog RTL Source Code or Netlist format
  • Testbenches
  • Integration examples
  • Software HAL & driver source code
  • Software example
  • Documentation
Evaluation License Evaluation for upcoming design  Valid for single-instance implementation/synthesis into one device (SoC, or FPGA) for a specific upcoming design project. Free, no license fee
  • Netlist format, time-bombed
  • Testbenches
  • Integration examples
  • Software HAL & driver source code
  • Software example
  • Documentation
Resource Utilization and Performance
Device

Logic

FF

fmax

Max. throughput

AMD Spartan 7

8165 LUTs

2810

174 MHz

11.4 Gbps

AMD Kintex-7 series

8151 LUTs

2811

258 MHz

16.5 Gbps

AMD Zynq MPSoC US+

8152 CLBs

2811

331 MHz

21.2 Gbps

Efinix Titanium

8459 LUT4

2778

391 MHz

25.0 Gbps

Effinix Trion

8459 LUT4

2778

90 MHz

5.8 Gbps

Lattice Avant E

11301 LUT4

2790

131 MHz

8.4 Gbps

Lattice CertusPro-NX

11948 LUT4

2804

149 MHz

9.5 Gbps

Lattice Certus-NX

11948 LUT4

2804

149 MHz

9.5 Gbps