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KiviHash-SHA-512/384 - Secure Hash Algorithm IP Core

IP Core Documentation

FPGA Implementation Results

 Licensing

KiviHash-SHA-512/384 Overview 

KiviHash-SHA-512/384 is an IP core implementing the SHA-384, SHA-512 and SHA512/256 cryptographic algorithm, an one-way hash function compliant to NIST’s FIPS 180-4 standard. It is optimized for high speed designs and easy integration with any FPGA and ASIC designs. Automatic byte padding is included. It features a standard AMBA® AXI4-Lite interface for straightforward hardware integration and HAL, and software driver (C-code, platform independent) for simple software integration. 

Key Features

  • NIST FIPS 180-4 compliant
  • Supports cryptographic hashing for
  • automatic padding
  • High-speed design
  • AMBA® AXI4-Lite
  • Fully synchronous design
  • HAL and software driver (C-code, platform independent)
  • For any FPGA and ASIC

Tests and Verification

  • NIST CAVS test vectors for SHA hash functions
  • Extended verification through simulation
  • FPGA integration and implementation tests
  • Unity tests for driver and whole IP Core

SHA-3-Block-Diagram-1

 

Applications & Use Cases

The SHA-512/384 IP core offers a versatile solution for maintaining data integrity and verifying authentication across various applications. 
  • Firmware Updates: Detecting tampered or corrupted update packages
  • FPGA bitstreams: Ensuring only trusted configurations are loaded
  • Communication protocols: TLS, IPsec, MAC-based authentication
  • External memory integrity: Protecting stored data in flash or external RAM

Next Steps

Download the product brief, request documentation, or schedule a technical discussion to review your architecture.

Download product brief
Schedule a technical discussion

Product Information

Licensing & Deliverables
Strich-2-thick
License type Purpose Scope Fee Deliverables
Product License Manufacture of products intended for commercial distribution. Valid for single-instance implementation/synthesis into one device (e.g., one type of SoC, or FPGA) for a specific project or product definition. Multiple instantiations refer to the physical realization of one IP core multiple times in one device. Product licenses for IP Cores include volume caps of 10,000 units for FPGAs. One-time fee 
  • System Verilog RTL Source Code or Netlist format
  • Testbenches
  • Integration examples
  • Simulation and synthesis scripts 
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Evaluation License Usability and evaluation for upcoming design  Valid for single-instance implementation/synthesis into one device (SoC, or FPGA) for a specific upcoming design project. Free, no license fee
  • Netlist format, time-bombed
  • Testbenches
  • Integration examples
  • Software HAL & driver source code
  • Software example source code
  • Documentation
Support and Maintenance
Strich-2-thick
  • Maintenance & updates of IP cores included
  • Rapid update/bug fix cycles
  • Integration support: Comprehensive documentation and integration examples 
  • Web-based support with response times within 8 hours (Mo-Fri)